Meltdown & Spectre - Kernel Side-Channel Attacks - CVE-2017-5754 CVE-2017-5753 CVE-2017-5715

Public Date:
Updated -
Status
Resolved
Impact
Important

Red Hat has been made aware of multiple microarchitectural (hardware) implementation issues affecting many modern microprocessors, requiring updates to the Linux kernel, virtualization-related components, and/or in combination with a microcode update.  An unprivileged attacker can use these flaws to bypass conventional memory security restrictions in order to gain read access to privileged memory that would otherwise be inaccessible. There are 3 known CVEs related to this issue in combination with Intel, AMD, and ARM architectures. Additional exploits for other architectures are also known to exist. These include IBM System Z,  POWER8 (Big Endian and Little Endian), and POWER9 (Little Endian).

Background Information

An industry-wide issue was found with the manner in which many modern microprocessor designs have implemented speculative execution of instructions (a commonly used performance optimization). There are three primary variants of the issue which differ in the way the speculative execution can be exploited. All three rely upon the fact that modern high performance microprocessors implement both speculative execution, and utilize VIPT (Virtually Indexed, Physically Tagged) level 1 data caches that may become allocated with data in the kernel virtual address space during such speculation.

The first two variants abuse speculative execution to perform bounds-check bypass (CVE-2017-5753), or by utilizing branch target injection (CVE-2017-5715) to cause kernel code at an address under attacker control to execute speculatively. Collectively these are known as "Spectre".  Both variants rely upon the presence of a precisely-defined instruction sequence in the privileged code, as well as the fact that memory accesses may cause allocation into the microprocessor’s level 1 data cache even for speculatively executed instructions that never actually commit (retire).  As a result, an unprivileged attacker could use these two flaws to read privileged memory by conducting targeted cache side-channel attacks. These variants could be used not only to cross syscall boundary (variant 1 and variant 2) but also guest/host boundary (variant 2).

The third variant (CVE-2017-5754) relies on the fact that, on impacted microprocessors, during speculative execution of instruction permission faults, exception generation triggered by a faulting access is suppressed until the retirement of the whole instruction block. Researchers have called this exploit "Meltdown".  Subsequent memory accesses may cause an allocation into the L1 data cache even when they reference otherwise inaccessible memory locations. As a result, an unprivileged local attacker could read privileged (kernel space) memory (including arbitrary physical memory locations on a host) by conducting targeted cache side-channel attacks.

Acknowledgements

Red Hat would like to thank Google Project Zero for reporting these flaws.

Additional References

Is CPU microcode available to address CVE-2017-5715 via the microcode_ctl package ?

Have questions? Watch the webinar on demand.

Find out more about the Speculative Store Bypass, which was announced in May 2018.

What are Meltdown and Spectre? Here’s what you need to know.

https://googleprojectzero.blogspot.ca/2018/01/reading-privileged-memory-with-side.html 

https://meltdownattack.com/

Speculative Execution Exploit Performance Impacts - Describing the performance impacts to security patches for CVE-2017-5754 CVE-2017-5753 and CVE-2017-5715Controlling the Performance Impact of Microcode and Security Patches for CVE-2017-5754 CVE-2017-5715 and CVE-2017-5753 using Red Hat Enterprise Linux Tunables

AMD Reccomendations for CVE-2017-5715

Additional Red Hat Product References

Options to address CVE-2017-5753 on XEN platform

Impacts of CVE-2017-5754, CVE-2017-5753, and CVE-2017-5715 to Red Hat Virtualization products

Impact of CVE-2017-5754, CVE-2017-5753, and CVE-2017-5715 to Red Hat OpenStack

Satellite 6 How to Provide Errata for Meltdown/Spectre to Content Hosts (CVE-2017-5753, CVE-2017-5754, and CVE-2017-5715)

Impacted Products

Red Hat Product Security has rated this update as having a security impact of Important.

The following Red Hat product versions are impacted:

  • Red Hat Enterprise Linux 5

  • Red Hat Enterprise Linux 6

  • Red Hat Enterprise Linux 7

  • Red Hat Atomic Host

  • Red Hat Enterprise MRG 2

  • Red Hat OpenShift Online v2

  • Red Hat OpenShift Online v3

  • Red Hat Virtualization (RHEV-H/RHV-H)

  • Red Hat Enterprise Linux OpenStack Platform 6.0 (Juno)

  • Red Hat Enterprise Linux OpenStack Platform 7.0 (Kilo) for RHEL7

  • Red Hat Enterprise Linux OpenStack Platform 7.0 (Kilo) director for RHEL7

  • Red Hat OpenStack Platform 8.0 (Liberty)

  • Red Hat OpenStack Platform 8.0 (Liberty) director

  • Red Hat OpenStack Platform 9.0 (Mitaka)

  • Red Hat OpenStack Platform 9.0 (Mitaka) director

  • Red Hat OpenStack Platform 10.0 (Newton)

  • Red Hat OpenStack Platform 11.0 (Ocata)

  • Red Hat OpenStack Platform 12.0 (Pike)

While Red Hat's Linux Containers are not directly impacted by kernel issues, their security relies upon the integrity of the host kernel environment. Red Hat recommends that you use the most recent versions of your container images. The Container Health Index, part of the Red Hat Container Catalog, can always be used to verify the security status of Red Hat containers. To protect the privacy of the containers in use, you will need to ensure that the Container host (such as Red Hat Enterprise Linux or Atomic Host) has been updated against these attacks. Red Hat has released an updated Atomic Host for this use case.

Attack Description and Impact

The attacks described in this article abuse the speculative execution capability of modern high-performance microprocessors. Modern microprocessors implement a design optimization known as “Out-of-Order” (OoO) execution, meaning the microprocessor will begin to execute independent instructions as soon as their data dependencies become available (so-called “data flow” model) rather than always executing instructions in the literal order provided by the programmer through their application binary. The illusion of a sequential execution is maintained within the processor by means of various internal reordering structures that buffer these intermediate execution states of the processor and present the in-order results. Out-of-Order (OoO) Execution was originally invented by Robert Tomasulo in 1967 for use in the early IBM mainframe systems. In the intervening decades, it has become a standard feature of nearly all microprocessors. 

An extension of the Out-of-Order execution model adds highly sophisticated branch prediction algorithms that aim to predict whether a given path (branch) of software code will be executed. A branch can be thought of as changing the flow of instructions being executed by the processor in response to an “if” statement of the form “if this, then do A, otherwise do B”. The condition upon which a branch is taken or not taken often depends upon data that may not immediately be available (for example, because it requires a load from slower RAM into the internal microprocessor cache hierarchy). Since the branch condition may not be ready in a timely manner, the processor may begin to speculatively execute the most likely path, based on input from the branch predictor. Results from this execution are stored in such a manner that the entire path can be discarded if the speculated branch direction later turns out to be incorrect. Thus, speculative execution is normally completely invisible to the programmer, or to other users of the same system.

The attacks described in this article rely upon breaking open the black box that is the internal state of the microprocessor during speculative execution. In particular, the attacks rely upon a technique known as cache side-channel analysis. During speculative execution, a processor will not intermediately make results available in memory or registers visible to the programmer, to other processors, or to other running applications. Yet, in order to access memory within speculated code paths, it must bring the data in the processor cache. Side-channel analysis allows an attacker to observe speculated allocations (loads) into the system caches, even those coming from execution paths that ultimately have been discarded. A specially crafted program can then be designed to speculatively perform loads into the cache from privileged memory locations, and monitor the results which can be used to infer the content of that privileged memory.

One case that triggers CPU speculative execution is branches. An attacker can start by training the branch predictor that a particular branch in kernel code is heavily taken (or not taken). The next time the branch executes, the processor will start executing the code in the direction chosen by the attacker. If the attacker chooses a path that loads a value from memory, such load will be executed speculatively.  Attacks against branch prediction can (in some affected microprocessor implementations) be extended across the kernel/hypervisor boundary, allowing unprivileged guest Operating Systems to exert influence over the execution of the hypervisor and, when combined with side-channel analysis, to extract sensitive hypervisor memory.

The effects of speculative execution however can be even more wide-ranging. Because the internal state of the microprocessor is not visible to the programmer, or to other users or applications running on the system, the processor may perform speculative data accesses even before checking whether they are permitted. Permission checks will occur in parallel and ultimately trigger an abort of the speculation prior to retiring the speculated instructions and making their execution results visible outside the processor. If the processor speculatively uses cached data from memory prior to completing the permission checks, then it becomes possible to observe that data by using it in subsequent memory accesses.

One example of such permission checks is page access checks from the memory management unit (MMU). Paging, also known as virtual memory, is a common feature of high performance microprocessors; it lets the operating system control the mapping of virtual addresses into the physical addresses of the system RAM, and also limit accesses to the virtual addresses through access control bits. For example, a page can be marked as “read-only” (so that writes cause a page fault exception) or as “kernel memory” (so that user-mode accesses cause a page fault exception).

Because the processor’s permission checks enforce that user applications cannot access kernel memory, it is standard practice in the industry for operating system kernels (including Linux) to map kernel virtual memory addresses into the same address space as user applications. Doing so creates a significant performance advantage since applications make frequent use of kernel-provided system calls, and switching address spaces during each system call would incur a significant performance overhead. Each switch would require flushing (invalidating) the content of many internal CPU structures, such as TLBs (Translation Lookaside Buffers) that cache virtual-to-physical memory translations and accelerate the use of virtual memory.

Sharing the page tables between the kernel and user applications, however, enables another kind of attack against speculative execution. In this case, the preparatory phase has the attacker trick the kernel into loading an “interesting” virtual address into the processor’s Level 1 (L1) data cache. The L1 data cache is commonly organized using a technique known as VIPT (Virtually Indexed, Physically Tagged), which lets the virtual-to-physical address translation and permission checks occur in parallel with access. In the presence of a shared virtual address space, kernel privileged virtual addresses might be accessed speculatively through the L1 cache by untrusted user code during speculative execution, and the loaded values can be used further down the speculatively-executed path. A second speculative memory access can thus fill the cache in a manner that depends on privileged memory contents, and the effects can be observed to derive those contents.

These microprocessor side-channel attacks may allow an untrusted user with access to a machine to extract sensitive information from privileged kernel or hypervisor memory, as well as from other applications or virtual machines running on the same system. Mitigation involves a number of discrete steps, some or all of which may be required depending upon the exact make and model of the microprocessor, each of which may be vulnerable to a differing extent to each variant of the attack:

  • Separating the kernel and user virtual address spaces: this is performed using a design change to the Operating System kernel known as KPTI (Kernel Page Table Isolation), sometimes referred to using the older name “KAISER”. 
  • Disabling indirect branch prediction upon entry into the kernel or into the hypervisor: New capabilities have been added to many microprocessors across the industry through microcode, millicode, firmware, and other updates. These new capabilities are leveraged by updates to Red Hat Enterprise Linux which control their use.
  • Fencing speculative loads of certain memory locations: Such loads have to be annotated through small changes to the Linux kernel, which have been integrated into Red Hat updates.

These software solutions, in combination with microcode, millicode, and firmware updates can mitigate the attacks described in this article. However, the mitigation comes at some cost to system performance. Depending upon the specific system, make, and model of the microprocessors, as well as the characteristics of the workloads, the performance impact can be significant. Red Hat is taking a proactive position that favors security over performance, while allowing users the flexibility to assess their own environment and make appropriate tradeoffs through selectively enabling and disabling the various mitigations.

The Red Hat Performance Engineering team has created a Knowledgebase article reporting observed performance impact for a variety of representative workloads, and describing options users can take to disable parts of the security fixes to regain the desired level of performance if the customer is confident their computers are physically isolated.  Additional performance data will be published as this incident develops.

The Red Hat Performance Engineering and Product Engineering teams have developed a Knowledgebase article detailing the tunables available to selectively enable or disable these new security features.

Additional guidance for subscribers using AMD-based systems can be found in this Knowledgebase article.

Detection & Diagnosis

Determine if your system is vulnerable

Red Hat has created a Labs app to assist in detection of exposure to these vulnerabilities.  Subscribers can use the following link to access our Labs tool.

Determine if your system is vulnerable. Use the detection script to determine if your system is currently vulnerable to this flaw. To verify the legitimacy of the script, you can download the detached GPG signature as well. The current version of the script is 3.0.

For subscribers running Red Hat Virtualization products, a Knowledgebase article has been created to verify OEM-supplied microcode/firmware has been applied.

Take Action

Red Hat customers running affected versions of the Red Hat products are strongly recommended to update them as soon as errata are available. Customers are urged to apply the appropriate updates immediately.  All impacted products should apply fixes to mitigate all 3 variants; CVE-2017-5753 (variant 1),  CVE-2017-5715 (variant 2), and CVE-2017-5754 (variant 3).

NOTES

  • Meltdown is the branded name for CVE-2017-5754 (variant 3)
  • Spectre is the branded name for the combined CVE-2017-5753 (variant 1) & CVE-2017-5715 (variant 2)
  • Due to the nature of changes required, a kpatch for customers running Red Hat Enterprise Linux 7.2 or greater will NOT be available.
  • Variant 2 can be exploited both locally (within the same OS) and through the virtualization guest boundary. Fixes require CPU microcode/firmware to activate.  Subscribers are advised to contact their hardware OEM to receive the appropriate microcode/firmware for their processor.  An additional Knowledgebase article is available with more details.
  • Carefully read the text of the Security Errata. Not all architectures had mitigations released initially. The x86_64 mitigations do not include Red Hat Enterprise Linux 6 32bit kernels.
  • For customers using Red Hat OpenStack Platform, an additional Knowledgebase article is also available.
  • For customers using Red Hat Satellite 6, an additional Satellite 6 Knowledgebase article is also available. NOTE: Please use the table below to help quickly identify the specific RHSA ID's that you want to apply to your systems.

CVE-2017-5754 (variant 3, aka Meltdown) patches for 32-bit Red Hat Enterprise Linux 5

Red Hat has no current plans to provide mitigations for the Meltdown vulnerability in 32-bit Red Hat Enterprise Linux 5 environments.

Following many hours of engineering investigation and analysis, Red Hat has determined that introducing changes to the Red Hat Enterprise Linux 5 environment would destabilize customer deployments and violate our  application binary interface (ABI) and kernel ABI commitments to customers who rely on Red Hat Enterprise Linux 5 to be absolutely stable.

Although Red Hat has delivered patches to mitigate the Meltdown vulnerability in other supported product offerings, the 32-bit Red Hat Enterprise Linux 5 environment presents unique challenges.  The combination of limited address space in 32-bit environments plus the mechanism for passing control from the userspace to kernel and limitations on the stack during this transfer make the projected changes too invasive and disruptive for deployments that require the highest level of system stability.  By contrast, 32-bit Meltdown mitigations have been delivered for Red Hat Enterprise Linux 6, where the changes are far less invasive and risky.

Updates for Affected Products

ProductPackageAdvisory/UpdateApplicable to Variant
Red Hat Enterprise Linux 7 (z-stream)kernelRHSA-2018:00071,2,3
Red Hat Enterprise Linux 7kernel-rtRHSA-2018:00161,2,3
Red Hat Enterprise Linux 7libvirtRHSA-2018:00292
Red Hat Enterprise Linux 7qemu-kvmRHSA-2018:00232
Red Hat Enterprise Linux 7dracutRHBA-2018:00422
Red Hat Enterprise Linux 7.3 Extended Update Support**kernelRHSA-2018:00091,2,3
Red Hat Enterprise Linux 7.3 Extended Update Support**libvirtRHSA-2018:00312
Red Hat Enterprise Linux 7.3 Extended Update Support**qemu-kvmRHSA-2018:00272
Red Hat Enterprise Linux 7.3 Extended Update Support**dracutRHBA-2018:00432
Red Hat Enterprise Linux 7.2 Update Services for SAP Solutions, & Advanced Update Support***,****kernelRHSA-2018:00101,2,3
Red Hat Enterprise Linux 7.2 Update Services for SAP Solutions, & Advanced Update Support***,****libvirtRHSA-2018:00322
Red Hat Enterprise Linux 7.2 Update Services for SAP Solutions, & Advanced Update Support***,****qemu-kvmRHSA-2018:00262
Red Hat Enterprise Linux 7.2 Update Services for SAP Solutions, & Advanced Update Support***,****dracutRHBA-2018:00622
Red Hat Enterprise Linux 6 (z-stream)kernelRHSA-2018:00081,2,3
Red Hat Enterprise Linux 6libvirtRHSA-2018:00302
Red Hat Enterprise Linux 6qemu-kvmRHSA-2018:00242
Red Hat Enterprise Linux 6.7 Extended Update Support**kernelRHSA-2018:00111,2,3
Red Hat Enterprise Linux 6.7 Extended Update Support**libvirtRHSA-2018:01082
Red Hat Enterprise Linux 6.7 Extended Update Support**qemu-kvmRHSA-2018:01032
Red Hat Enterprise Linux 6.6 Advanced Update Support***,****kernelRHSA-2018:00171,2,3
Red Hat Enterprise Linux 6.6 Advanced Update Support***,****libvirtRHSA-2018:01092
Red Hat Enterprise Linux 6.6 Advanced Update Support***,****qemu-kvmRHSA-2018:01042
Red Hat Enterprise Linux 6.5 Advanced Update Support***kernelRHSA-2018:00221,2,3
Red Hat Enterprise Linux 6.5 Advanced Update Support***libvirtRHSA-2018:01102
Red Hat Enterprise Linux 6.5 Advanced Update Support***qemu-kvmRHSA-2018:01052
Red Hat Enterprise Linux 6.4 Advanced Update Support***kernelRHSA-2018:00181,2,3
Red Hat Enterprise Linux 6.4 Advanced Update Support***libvirtRHSA-2018:01112
Red Hat Enterprise Linux 6.4 Advanced Update Support***qemu-kvmRHSA-2018:01062
Red Hat Enterprise Linux 6.2 Advanced Update Support***kernelRHSA-2018:00201,2,3
Red Hat Enterprise Linux 6.2 Advanced Update Support***libvirtRHSA-2018:01122
Red Hat Enterprise Linux 6.2 Advanced Update Support***qemu-kvmRHSA-2018:01072
Red Hat Enterprise Linux 5 Extended Lifecycle Support*kernelRHSA-2018:0292

1,2,3

Red Hat Enterprise Linux 5.9 Advanced Update Support***kernelRHSA-2018:04641,3
RHEL Atomic HostkernelImages respun on 5 January 20181,2,3
Red Hat Enterprise MRG 2kernel-rtRHSA-2018:00211,2,3
Red Hat Virtualization 4 (RHEV-H/RHV-H)redhat-virtualization-hostRHSA-2018:00471,2,3
Red Hat Virtualization 4 (RHEV-H/RHV-H)rhvm-applianceRHSA-2018:00451,2,3
Red Hat Virtualization 4 (RHEV-H/RHV-H)qemu-kvm-rhevRHSA-2018:00252
Red Hat Virtualization 4 (RHEV-H/RHV-H)vdsmRHSA-2018:00502
Red Hat Virtualization 4 (RHEV-H/RHV-H)ovirt-guest-agent-dockerRHSA-2018:00472
Red Hat Virtualization 4 (RHEV-H/RHV-H)rhevm-setup-pluginsRHSA-2018:00512
Red Hat Virtualization 3 (RHEV-H/RHV-H)redhat-virtualization-hostRHSA-2018:00441,2,3
Red Hat Virtualization 3 ELS (RHEV-H/RHV-H)rhev-hypervisor7RHSA-2018:00461,2,3
Red Hat Virtualization 3 ELS (RHEV-H/RHV-H)qemu-kvm-rhevRHSA-2018:00282
Red Hat Virtualization 3 ELS (RHEV-H/RHV-H)vdsmRHSA-2018:00482
Red Hat Virtualization 3 ELS (RHEV-H/RHV-H)rhevm-setup-pluginsRHSA-2018:00522
Red Hat Enterprise Linux OpenStack Platform 6.0 (Juno) for RHEL7qemu-kvm-rhevRHSA-2018:00542
Red Hat Enterprise Linux OpenStack Platform 7.0 (Kilo) for RHEL7qemu-kvm-rhevRHSA-2018:00552
Red Hat Enterprise Linux OpenStack Platform 7.0 (Kilo) director for RHEL7director imagesRHBA-2018:00641,2,3
Red Hat OpenStack Platform 8.0 (Liberty)qemu-kvm-rhevRHSA-2018:00562
Red Hat OpenStack Platform 8.0 (Liberty)director imagesRHBA-2018:00651,2,3
Red Hat OpenStack Platform 9.0 (Mitaka)qemu-kvm-rhevRHSA-2018:00572
Red Hat OpenStack Platform 9.0 (Mitaka)director imagesRHBA-2018:00691,2,3
Red Hat OpenStack Platform 10.0 (Newton)qemu-kvm-rhevRHSA-2018:00582
Red Hat OpenStack Platform 10.0 (Newton)director imagesRHBA-2018:00671,2,3
Red Hat OpenStack Platform 11.0 (Ocata)qemu-kvm-rhevRHSA-2018:00592
Red Hat OpenStack Platform 11.0 (Ocata)director imagesRHBA-2018:00681,2,3
Red Hat OpenStack Platform 12.0 (Pike)qemu-kvm-rhevRHSA-2018:00602
Red Hat OpenStack Platform 12.0 (Pike)director imagesRHBA-2018:00661,2,3
Red Hat OpenStack Platform 12.0 (Pike)containersRHBA-2018:00701,2,3


*An active ELS subscription is required for access to this patch.  Please contact Red Hat sales or your specific sales representative for more information if your account does not have an active ELS subscription.

**An active EUS subscription is required for access to this patch.  Please contact Red Hat sales or your specific sales representative for more information if your account does not have an active EUS subscription.

What is the Red Hat Enterprise Linux Extended Update Support Subscription?

***An active AUS subscription is required for access to this patch in RHEL AUS.

What is Advanced mission critical Update Support (AUS)?

****An active TUS subscription is required for access to this patch in RHEL TUS.

***** Subscribers should contact their hardware OEMs to get the most up-to-date versions of CPU microcode/firmware.

Mitigation

There is no known mitigation, other than applying vendor software updates combined with hardware OEMs CPU microcode/fiirmware. All Red Hat customers should apply vendor solutions to patch their CPUs, and update the kernel as soon as patches are available.

Customers are advised to take a risk-based approach in mitigating this issue.  Systems that require high degrees of security and trust should be addressed first, and should be isolated from untrusted systems until such time as treatments can be applied to those systems to reduce the risk of exploit.

Customers running Xen hypervisors should be aware of technical limitations of that software that cannot completely eliminate the variant 2 exploit, and cannot eliminate the variant 3 exploit on paravirtualized guests.  Red Hat has prepared a Knowledgebase article detailing the Xen situation and options available to Xen hypervisor users.

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47 Comments

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As I understand from https://access.redhat.com/articles/3311301 : The way to check that patching is effective is to verify that the values of /sys/kernel/debug/x86/ibrs_enabled and /sys/kernel/debug/x86/ibpb_enabled are both 1 after yum update + reboot. On RHEL 6, debugfs has to be actively mounted for /sys/kernel/debug/x86 to be present. One may choose to turn off ibrs and ibpb as a performance/security trade-off, though. We are seeing some servers where values are 0 after yum update + reboot, and that seems to be because microcode_ctl doesn't contain any microcode for the CPU being used. For this, we have to wait for someone (Intel?) to push microcode to the microcode_ctl project, I suppose.

But for a production system where it's difficult to get a maintenance window, it would be nice to know beforehand if microcode_ctl will be able to do its magic. In other words: It's problematic to negotiate a maintenance window and then have to report back that it was not fully effective. So, specifically: For an RHEL 7.4 server which has not been patched for Spectre/Meltdown yet, how do I determine whether ibrs_enabled/ibpb_enabled can be expected to be 1 after yum update + reboot?

Hey, So , for this burning and newborn vulnerability , updating the kernel in bare metal as well as VM guests will erradiate the problem or any other measures also needs to be taken from Physical box side as well ? Physical boxes refer to bare metal servers ( intel, amd ,etc ) Please let me know. Thanks in advance !

Raghavan,

Kernel updates are half of the solution. BIOS/Firmware updates must be paired with the kernel updates. Red Hat is providing microcode updates for a small subset of tested processors. Dell has this to say at support.dell.com...

"Dell is aware of the new side-channel analysis attacks (also known as Meltdown and Spectre) affecting many modern microprocessors. We are working with Intel and others in the industry to investigate and address the issue. For more information, please refer to our Knowledge Base articles for Client products and for Servers."

"There are two essential components that need to be applied to mitigate the above mentioned vulnerabilities: 1) System BIOS as per Tables below, and 2) Operating System/Hypervisor updates. We encourage customers to review the appropriate Hypervisor/OS vendor security advisory. The References section below contains links to some of these vendors."

At this time PowerEdge 14 and 13 generation BIOS updates are available. I am waiting on 12 and 11 gen, too.

Is this issue with Xen + el6 kernel-2.6.32-696.18.7.el6.x86_64 also being tracked by Red Hat?
https://bugs.centos.org/view.php?id=14336

CentOS forum thread here:
https://www.centos.org/forums/viewtopic.php?f=13&t=65602&start=10

Is there any patches for RHEL5.x ?????????????????????????????????????

Posted by Chris earlier in this tread.

Christopher Robinson We will be pushing errata out as soon as they have passed our QA team's testing. The more modern versions were easier to backport patches from upstream, and as you progress backwards the fixes change from a backporting exercise into a complete rewrite. We expect all packages for RHEL7 to be available shortly, with RHEL6 following closely behind. Our layered products will be respinning now that the signed packages are available, so products like OpenStack or RHEL Atomic will be available within a few days. RHEL5 should be complete in the next week or so, but working with 10+ year old code we are very cautious about ensuring there are no unforeseen regressions the newer code could introduce. Our goal is to provide the necessary fixes and be as minimally invasive as possible to that older code to ensure that it continues to work consistently and stably as our subscribers expect it to.

Any ETA for RH5 that can be shared?

We are continuing to work on creating patches that address our supported versions of RHEL5. They will be posted as soon as they finsih QE testing. When they are available this page will be updated and advisories will be sent out to subscribers.

We have servers that were not deployed with micorcode_ctl. In this case, should I follow with your installation.

I see new kernel and fixes for RHEL 6.7, 6.9, 7.x... but I dont see the kernel for 6.8 Can you make the fix to the 2.6.32-642.... kernel and others for use with RHEL 6.8 ?

Thanks in advance.

RHEL6.8 is not a currently supported version of Red Hat Enterprise Linux. Fixes are available for our current z-stream (6.9z) and EUS channel (6.7). No fixes will be issued to the RHEL6.8 channel.

If the latest release of RHEL6 is 6.9, why is it that RHEL6.8 is not supported, and instead 6.7 is? Should not this be part of EUS by definition? This worries me, as we have a number of RHEL6.8 servers that would need a fix in some form.

Thanks.

Should not this be part of EUS by definition

Gustavo: not every minor release of RHEL has a EUS update channel associated with it.

From what I understand installing the fixes on intel based system will cause a performance impact but I wonder if the KPTI patches are in effect on AMD also? I mean, will AMD have the same performance impact as Intel or will different code path be used on AMD?

When RHEL 7.1 packages will be available?

Jason - RHEL7.1 is not a currently supported offering. If you have a current subscription you can access fixes for RHEL7.4z or 7.3EUS.

Is there a command to verify before and after I apply yum update on 7.4 that correct patches for CVEs were applied?

Saad - yes, from an OS-perspective you will have applied the correct fixes. You should still contact your CPU vendor to get the appropriate CPU microcode/firmware/millicode to ensure you are activating the Variant 2 fixes. At this time, Red Hat does not have an exhaustive list of updated CPU code from our partners. The best source is the manufacturer of your microprocessor.

Our Insights team is working on a detection script to validate the appropriate patches have been applied. Look for an update to the Diagnostic tab of this article in the coming days to supply that.

thank you Christopher!

Here's Intel's download page for microcode:

https://downloadcenter.intel.com/download/27431/Linux-Processor-Microcode-Data-File

Hello,

could you please confirm if we can rely on this script to check the status of our systems? Is it interpreting RHEL 6 and 7 kernels correctly? https://github.com/speed47/spectre-meltdown-checker

It could be particularly useful to check those systems not yet provided with an updated firmware from the hardware vendor.

Thank you very much.

I was looking at the response from upstream QEMU here: https://www.qemu.org/2018/01/04/spectre/ and I wasn't sure if they were referring to updates that Red Hat put in place with the qemu-kvm updates they released or not.

After applying the qemu-kvm updates for RHEL 6 or RHEL 7 provided by Red Hat, is it sufficient if guests are just live migrated to systems that have the updates installed? Or is it necessary to shut down and start back up each guest so it picks up the updates (as indicated in the QEMU response above)?

Thanks!

Hello,

I could see the updated patches for 7.2, 7.3 & 6.8..

Could you please confirm how can I download all patches (kernel + dependent) instead of one by one?

Thanks.

Hi, - 7.2 is an already end of life EUS stream and no fixes are being made available to EUS customers within the 7.2 stream. - 7.3 already has fixes released within the EUS stream. If you do not have access to EUS product, please contact your Red Hat account rep. - 6.8 has never had an active support stream, such as EUS. When 6.9 was released the main zstream channel moved straight from 6.8 to 6.9. Regards,

It is supposed to update VM guest OS as well so you'll have to power cycle it anyway.

Matt the libvirt and qemu packages we have released include all the code that upstream qemu has published. Our engineer was the one that helped create them and is our upstream maintainer.

hi, I can't see any patches for RHEL 7.2 EUS. When can I expect patches for our 7.2 Systems?

Hi, The 7.2 EUS stream has already hit the end of life. There is no plans to release packages for mitigation within the 7.2 EUS channel. Please consider updating to a supported content stream that you have available to yourself.

Regards,

sorry , but 7.2 EUS isn't end of life at all.

Hi,

Question. After patching, the parameters have become available and are set to 1 by default. I know that via # echo 0 > /sys/kernel/debug/x86/pti_enabled I can set it at runtime, but this of course is not boot-proof. I do not want to change the grub config, yet. I tried to include the change in tuned.conf and /etc/sysctl.conf, but I do not see any changes after activating the according profile or via sysctl -p. Where do I put pti_enabled = 0 ibpb_enabled = 0 ibrs_enabled = 0 ?? Running RHEL 7.4.

Hello There,

With kernel update for RHEL 7.4 through " 3.10.0-693.11.6.el7.x86_64" we are getting * ibpb, ibrs disabled (0) * pti enabled (1) The explanation about these debug fs tunables in article - https://access.redhat.com/articles/3311301 suggests that these 3 must be enabled to mitigate the Speculative execution. My question is when RedHat providing the kernel patch shouldn't these tuneables come enabled by default or does it depends on CPU architecture of my machine ?
Infact the security advisory doc not stating anything to enable/disable post kernel update. Please shed some light on it.

Thanks RR

Do you guys have any tools that we can use to monitor CPU/Memory performance before/after we apply the patches?

Than you.

When I do a 'yum update' for release 7.3, I get kernel 3.10.0-514.26.2 and not 3.10.0-514-36.5. Is it still not available via 'yum update' ?

Hi, I'd say there is a small error in the check script in check_variants_runtime(): "if (( pti_enabled == 1 && ibpb_enabled == 1 && ibrs_enabled == 1 )); then"

ibrs_enabled can also be 2 (1=kernel space 2=kernel and userspace) to be mitigated; 1 is just the rhel default

Greetings Klaas

Hi Klaas. You are right. The script has been updated. Thank you.

For those looking for the sysctl tunables (after applying all your patches/microcode).. they seem to be:

echo 1 > /sys/kernel/debug/x86/pti_enabled
echo 1 > /sys/kernel/debug/x86/ibpb_enabled
echo 1 > /sys/kernel/debug/x86/ibrs_enabled

But they very well could impose a performance hit.. so test with "echo 0".. then "echo 1".. then if acceptable.. commit to /etc/sysctl.conf

Am I off base here Cliffy / Christopher?

Tweeks

Hi Tweeks, We detail this within article: Controlling the Performance Impact of Microcode and Security Patches for CVE-2017-5754 CVE-2017-5715 and CVE-2017-5753 using Red Hat Enterprise Linux Tunables - https://access.redhat.com/articles/3311301

In short you are correct. If the ibrs though is set to 0 and you attempt to flip it to enabled '1' and get a write error it is an indicator that your microcode/firmware has not been updated yet and does not support this capability. Regards, Cliff

It seems like the check logic in the script may be reversed, based on the performance tuning page: From: https://access.redhat.com/articles/3311301

AMD Defaults: Due to the differences in underlying hardware implementation, AMD X86 systems are not vulnerable to variant #3. The correct default values will be set on AMD hardware based on dynamic checks during the boot sequence.

pti 0 ibrs 0 ibpb 2 -> fix variant #1 #2 if the microcode update is applied

pti 0 ibrs 2 ibpb 1 -> fix variant #1 #2 on older processors that can disable indirect branch prediction without microcode updates

The Logic in the script is reversed:

            if (( pti_enabled == 0 && ibpb_enabled == 0 && ibrs_enabled == 2 )); then

                variant_2="Mitigated"

            fi

            if (( pti_enabled == 0 && ibpb_enabled == 2 && ibrs_enabled == 1 )); then

                variant_2="Mitigated"

Note that ibpb_enabled in the tuning should be "1" and ibrs_enabled should be "2", but the script is looking for ibpb_enabled == 2 and ibrs_enabled == 1. Which is right?

FWIW, my older AMD server after patching matches the tuning document, but the script still says vulnerable.

You are right, there was a mistake in flag order in the script. I am sorry about it. It should be fixed now. Thanks for noticing!

The checker script in the Diagnose could be better e.g. RHEL6 is does not mount debugfs - I found this one https://github.com/speed47/spectre-meltdown-checker much more comprehensive and also gives output for nrpe, json which is useful for nagios, puppet, ansible etc.

Hi Andrew. Thanks for your feedback! When debugfs is not mounted, the script uses fallback detection by reading dmesg. The return code uses a binary flags for different variants (2 for #1, 4 for #2, and 8 for #3) which should be enough for check automation through tools.

Also thanks for pointing out the spectre-meltdown-checker, it seems to be very well done.

Intel released the warning that there can be some glitch in recent CPU microcodes. It's said that it may be the cause of sudden reboots on Broadwell/Haswell platforms: newsroom.intel.com/news/intel-security-issue-update-addressing-reboot-issues/

Does it affect also microcodes already released in the latest microcode_ctl erratas RHSA-2018:0012 and RHSA-2018:0013?

Yes it does. https://access.redhat.com/solutions/3315431 has a list of the CPUs that are included in the microcode_ctl package.

But the latest microcode update from Intel was released after mentioned erratas. It has 20180108 release date, but erratas RHSA-2018:0012 and RHSA-2018:0013 were released on 20180103.

So it may not be identical and could have been created from some previous non-public release. In that case it can be OK, if the glitch comes from some later performance optimizations.

I've verified, and the three updates that were included in microcode_ctl-2.1-22.2.el7 and microcode_ctl-1.17-25.2.el6_9 (06-3f-02, 06-4f-01, 06-55-04) are the same as those issued by Intel in their bundle released on 20180108.

Yes Jaroslav the microcode we originally were given by our provider will contain the same possibly for problems on Broadwell and Hasswell chips. We are in the process of removing that software and, as we've been encouraging all along, are advising our subscribers to contact the OEM manufacturer of their systems' CPUs to get the appropriate software for their chip.

Is there a bugzilla for this?

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