DesignWare PHY IP Synopsys' comprehensive portfolio of high performance, low power mixed-signal PHY IP for the PCI Express, SATA, XAUI and USB protocols, enable designers to quickly integrate high performance interfaces into their next-generation SoCs while minimizing power consumption. Designed with low power in mind, all of the DesignWare PHY IP is built with a high performance architecture that provides low area and up to half the power compared to competitive solutions. The Synopsys DesignWare USB IP now provides support for the USB 2.0 Link Power Management (LPM) and High Speed Inter-Chip (HSIC) standards. The DesignWare USB LPM and HSIC IP reduces power consumption and area for USB-enabled designs. LPM defines a new sleep state to provide faster suspend and resume times and HSIC eliminates the USB connectors and cables, thus simplifying the USB connection down to two wires.