Signoff users generally have four key solution requirements in order to meet their design requirement needs:
continuous improvement to runtime and capacity to address increasing chip size requirements, efficient multi-scenario analysis to verify timing across all corners and modes, margin control to reduce over-design and maximize chip performance, and accuracy to insure correlation to silicon. The Synopsys PrimeTime® Suite addresses these requirements by delivering fast, memory-efficient scalar and multicore computing, distributed multi-scenario analysis and ECO fixing, using advanced constraint analysis, and variationaware Composite Current Source (CCS) modeling that extends static timing analysis to include Crosstalk Timing, Noise, Power and statistical STA.