Synopsys' Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer's ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality.