IC Validator is a signoff DRC / LVS tool that has been architected and proven for in-design physical verification at leading-edge process nodes. It delivers excellent scalability for efficient utilization of available hardware, superior ease-of-use for the physical designer, and high programmability for easier runset development. IC Validator’s high performance DRC and LVS physical verification engine substantially reduces the time to results through near-linear scalability across multiple CPU cores. IC Validator is seamlessly integrated with IC Compiler for In-Design physical verification. This award-winning technology accelerates design closure for manufacturing by enabling independent signoff quality analysis and automatic repair, including Double Patterning Technology (DPT) decomposition checking — all within the implementation environment. IC Validator is fully qualified and silicon proven by major foundries and IDMs for physical signoff at advanced nodes.