The Certify software is the leading implementation and partitioning tool for ASIC designers who use FPGA-based prototypes to verify their designs. The Certify software provides a quick and easy method for conversion and partitioning of large ASIC designs onto multi-FPGA prototyping boards and includes powerful features that make it easy to adapt to existing device flows – speeding the validation process and helping to ease time-to-market challenges. The Certify tool works seamlessly with HAPS FPGA-based prototyping systems and offers additional and exclusive features for the Synopsys HAPS prototyping system minimize prototype bring-up times and higher system performance. Key Features Includes easy-to-use graphical user interface (GUI) flow guide Automatic mapping of ASIC style RTL source code and DesignWare® IP to multiple FPGAs Allows automatic and/or manual partitioning Next-generation Swarm Intelligence Partition Engine (SWIPE) finds more feasible partition solutions Impact analysis interface provides immediate FPGA resource consumption feedback during interactive partitioning Supports Synopsys Design Constraints for timing management Supports multicore parallel processing for faster runtimes Supports FPGA devices popular for FPGA-based prototyping Includes industry standard Synplify® Premier synthesis engine Includes Identify® RTL Debugger for simulator-like visibility into FPGA hardware HAPS-Specific Features Includes library of HAPS®-50/60/70 series motherboard and daughter board descriptions for immediate planning and implementation Quickly bring-up multi-system prototypes with Tcl-based system target scripts Offers High-Speed Time Domain Multiplexing (HSTDM) I/O sharing to increase FPGA interconnection bandwidth Multi-chip, system-level static timing analysis for accurate prototype performance reviews