HyperFault Mixed-Level Fault Simulator is a Verilog IEEE-1364-2001 compliant fault simulator that analyses test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing. HyperFault’s proven algorithms enable efficient multi-pass fault simulation over distributed CPUs to achieve accurate results with excellent runtime performance. Key Features Verilog HDL IEEE 1364-2001 compliant fault simulator Uses standard Verilog source files and libraries for mixed-level fault simulation with gate, behavioral and switch devices Complements BIST and ATPG in finding interconnect faults for critical missions Efficient multi-pass concurrent fault simulation algorithm with iterative fault collapsing gives optimal memory allocation, excellent runtime performance and accurate fault detection Automatic design partitioning supports distributed CPUs with load balancing for fast grading of large designs Accurate fault grading models include stuck-at high/low output and input faults Full timing fault simulation encompasses SDF back annotation for post-route delay analysis