< Back to list

HIPEX Full-Chip Parasitic Extractor

HIPEX Full-Chip Parasitic Extraction products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology. They are tightly integrated with the Expert Layout Editor for the complete design flow of DRC/LVS/LPE and RC parasitic extraction on one platform. Key Features Accurate and fast full-chip hierarchical extraction software Capacitance - extracts accurate parasitic overlap, lateral, and fringe Resistance - extracts parasitics for lines, contacts, and vias;splitting long conducting tracks for accurate RC-distribution Selected net extraction for fast C and R extraction of critical path nets in SoCs and large memories Multiple parasitic extraction models to trade off between accuracy and run time Powerful scripting capabilities within technology files Output parasitic netlist files in SPICE, back-annotated netlist, DSPF and SPEF formats Efficient network reduction for distributed parasitic RC networks Tightly integrated with Expert Layout Editor or used in stand alone operation

Industry

Horizontal Industrial R&D

Red Hat Certifications

This product has been certified to run on the following Red Hat products and technologies:

Target Product Level
Red Hat Enterprise Linux 5.x Self-Certified
Red Hat Enterprise Linux 6.x Self-Certified