Guardian DRC/LVS/LPE Physical Verification products provide interactive and batch mode verification of analog, mixed signal and RF IC designs. Seamlessly integrated with Simucad schematic capture and layout editor, these tools efficiently perform design rule checks (DRC), layout vs. schematic (LVS) comparisons, and layout parameter extractions (LPE). Key Features Seamless integration with Expert Layout and Gateway Schematic Editors to provide a complete entry-to-verification design flow for analog, mixed-signal and RF designs Supports Mentor and Cadence Legacy™ DRC/LVS/LPE rule files with fast translation of Calibre™, Dracula™, and Diva™ Broad support of semiconductor process technologies through foundry-proven process design kits (PDKs) Fast, intuitive and hierarchical LVS debugging with netlist cross-probing Easily adopted by new users and seasoned professionals alike Same environment and support for Solaris, Linux, and Windows enables wide-scale deployment Multi-threading shortens the verification cycle by distributing load across multiple processors Accurate layout parameter extraction supports complex devices