AccuCore
Silvaco Data Systems Inc.
AccuCore Transistor and Gate Level Full-Chip STA with Automatic Block Characterization provides Static Timing Analysis (STA) of complex designs with mixed design styles. It gives designers the ability to characterize a multi-million transistor design with SmartSpice accuracy and perform block or full-chip static timing analysis. Key Features: Complete Static Timing Analysis (STA) environment quickly identifies timing bottlenecks leveraging state-dependent models Automated False Path removal addresses bi-directional transistors Easy setup enables mixing of custom and ASIC blocks in SoC environment Automatically partitions multi-million transistor, flat or hierarchical design with parasitics into Design Clusters for accurate SPICE level characterization Largest collection of calibrated SPICE models for CMOS and SOI, including BSIM3, BSIM3SOI, BSIM4, PSP, and HiSIM Produces timing models for Cadence and Synopsys PrimeTime® Generates fully-sensitized SPICE deck for critical paths and clock trees
Industry
Red Hat Certifications
This product has been certified to run on the following Red Hat products and technologies:
| Target Product | Level |
|---|---|
| Red Hat Enterprise Linux 5.x | Self-Certified |
| Red Hat Enterprise Linux 6.x | Self-Certified |
