Riviera-PRO is a multi-platform, high-performance, mixed-language RTL and gate-level simulator for ASIC and FPGA designs. It includes advanced debugging tools and support of advanced verification methodologies based on SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking. Riviera-PRO works in command line mode and in GUI with easy switching between the two. Top Features: ALINT Linting: 200 VHDL, Verilog & Clock Domain Crossing (CDC) design rules, synthesis emulation, violation viewer and configuration manager. Assertion and Coverage:based verification: Assertion & Cover viewers waveform /coverage and breakpoint editor. SystemVerilog IEEE 1800 Assertions/Coverage, PSL and Open Vera (OVA). Co-Simulation: DSP/HDL algorithm MATLAB and Simulink Interfaces. Code Coverage, Toggle & Functional Coverage. Debugging: Code execution/tracing, waveform compare, memory viewer, coverage, breakpoint editor, Xtrace, Advanced Dataflow, Profiler and SystemC co-debugging . Supported Languages: VHDL, Verilog, SystemVerilog IEEE Design/Verification/Assertions, SystemC and EDIF. SystemC Support: SystemC/C/C++ and HDL co-debugging in one simulation environment including tracing sourc code, setting breakpoints, viewing objects no matter what language was used.