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HES 2011

HES™ is a complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and prototyping. Top Features: Bit-Level Simulation Acceleration SoC HW/SW Co-Verification Transaction Level Emulation with SCE-MI 2.0, SystemC/C/C++, TLM2.0 Extensive Debugging (static/dynamic probes, memory access using GUI & API) Fully Scriptable Environment RTL Simulator Interfaces: Active-HDL™, NC-Sim®, ModelSim®, Riviera-PRO™, QuestaSim® and VCS-MX® Off-the-shelf FPGA prototyping boards support (Aldec HES-5, Dini Group®, Synopsys® HAPS™) Custom-in-house FPGA prototyping boards support Virtual Modeling with Imperas® OVP™ and OVPsim™ Linux and Windows® 32/64 bit support

Industry

Electronic Design Automation IT Infrastructure

Red Hat Certifications

This product has been certified to run on the following Red Hat products and technologies:

Target Product Level
Red Hat Enterprise Linux 6.x Self-Certified