ALINT 2012.01 SR1
Aldec, Inc.
ALINT™ is design analysis tool that identifies critical design issues early in the design stage of ASIC and FPGA designs. The tool points out coding style, functional, and structural problems in Verilog®, VHDL, and mixed-language designs, and prevents them from spreading into the downstream stages of your design flow. Sophisticated static analysis techniques uncover a variety of hidden bugs at the right time when cost and efficiency of modifications are optimal, and highly reduce the risks of redundant design iterations and costly re-spins. Top Features: Fast design analysis of complex ASIC/FPGA/SOC designs Phase-Based Linting (PBL) Methodology IEEE VHDL, Verilog and mixed-language designs STARC VHDL or Verilog rule plug-ins DO-254/ED-80 VHDL or Verilog rule plug-ins RMM rule plug-in (both Verilog and VHDL) Custom rule creation (C++ API) Integrated result analysis and debugging environment
Industry
Red Hat Certifications
This product has been certified to run on the following Red Hat products and technologies:
| Target Product | Level |
|---|---|
| Red Hat Enterprise Linux 6.x | Self-Certified |
