Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
Top Features:
High Performance Simulation
Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations
The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems
Complete support for the latest Verification Libraries, including Universal Verification Methodology (UVM)
Advanced Debugging
Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs quickly
Built-in debugging tools provide code tracing, waveform, data ow, coverage, assertion, and memory visualization capabilities
Comprehensive Assertion-Based Verification (SVA and PSL) for increased design observability and decreased debug time
Advanced Code and Functional Coverage capabilities and Coverage analysis tools for fast metric-based verification closure
Industry’s Best ROI
Riviera-PRO enables Aldec customers to deliver innovative products at a lower cost in shorter time
Features partnerships and integrations necessary to build complete design and verification flows
Deployment of any Aldec solution is accompanied by comprehensive training and support
Industry
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Red Hat Certifications
This product has been certified to run on the following Red Hat products and technologies:
| Target Product | Level |
|---|---|
| Red Hat Enterprise Linux 6.x | Self-Certified |
| Red Hat Enterprise Linux 5.x | Self-Certified |
