Design Rule Checking

ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents those issues from spreading into the downstream stages of design flow. The tool features highly customizable and intuitive framework that seamlessly integrates into existing environments and helps to automate any existing design guidelines. The framework delivers configurable sets of rules, efficient Phase-Based Linting (PBL) methodology, and feature rich result-analysis tools that significantly improve user productivity and overall efficiency of the design analysis and refinement process.

Top Features:
Fast design analysis of complex ASIC/FPGA/SOC designs
Phase-Based Linting (PBL) Methodology
IEEE VHDL, Verilog and mixed-language designs
STARC VHDL or Verilog rule plug-ins
DO-254/ED-80 VHDL or Verilog rule plug-ins
RMM rule plug-in (both Verilog and VHDL)
Custom rule creation (C++ API)
Integrated result analysis and debugging environment