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3.3. Using Makefiles

To build complex programs that consist of a number of source files, make uses configuration files called Makefiles that control how to compile the components of a program and build the final executable. Makefiles can also contain instructions for cleaning the working directory, installing and uninstalling program files, and other operations.
make automatically uses files named GNUmakefile, makefile, or Makefile in the current directory. To specify another file name, use:
make -f make_file
Describing the details of Makefile syntax is beyond the scope of this guide. See GNU make, the official GNU make manual, which provides an in-depth description of the GNU make utility, Makefile syntax, and their usage.
The full make manual is also available in the Texinfo format as a part of your installation. To view this manual, type:
~]$ scl enable devtoolset-6 'info make'

Example 3.2. Building a C Program Using a Makefile

Consider the following universal Makefile named Makefile for building the simple C program introduced in Example 3.1, “Building a C Program Using make”. The Makefile defines some variables and specifies four rules, which consist of targets and their recipes. Note that the lines with recipes must start with the TAB character:
CFLAGS=-c -Wall

all: $(SOURCE) $(EXE)

$(EXE): $(OBJ) 
        $(CC) $(OBJ) -o $@

        $(CC) $(CFLAGS) $< -o $@

        rm -rf $(OBJ) $(EXE)
To build the hello.c program using this Makefile, run the make utility:
~]$ scl enable devtoolset-6 'make'
gcc -c -Wall hello.c -o hello.o
gcc hello.o -o hello
This creates a new object file hello.o and a new binary file called hello in the current working directory.
To clean the working directory, run:
~]$ scl enable devtoolset-6 'make clean'
rm -rf hello.o hello
This removes the object and binary files from the working directory.